1. Technical Field
The present invention relates to computer software and, more particularly, to methods for classifying an integrated circuit or central processing unit version type via a JTAG scan chain.
2. Description of Related Art
Presently, a trend exists towards smaller electronic components which has resulted in higher component density and greater circuit complexity on a given-sized circuit board. The increase in circuit complexity has increased the difficulty of accomplishing in-circuit testing by physically accessing the circuits with a test fixture so that the response of the circuits to an external stimulus can be sensed. Indeed, as surface-mounted components (i.e., components which are mounted on a major surface of the circuit board) proliferate, physical access to the circuits on the board by traditional test fixtures may become impossible. For these reasons, much effort has been devoted to developing alternative testing techniques.
A testing technique known as xe2x80x9cboundary scanxe2x80x9d has gained prominence as an alternative to traditional in-circuit testing by physically accessing the board through a test fixture. The boundary scan testing technique is embodied in a detailed specification (Version 2.0) authored by an international standards committee known as the Joint Test Action Group (JTAG).
Accomplishing boundary scan testing requires that in addition to its normal application logic, each active component (e.g., integrated circuits) be fabricated with circuits known as xe2x80x9cboundary scan cellsxe2x80x9d (BSCs) whose details are described in the JTAG standard. Each BSC is coupled between the application logic and one of the functional input and output pins of the integrated circuit such that each functional input and output pin is coupled to a separate one of a normal data input and normal data output, respectively, of the BSC.
During normal operation of the integrated circuit, the signal applied to each functional input pin passes through the corresponding BSC and then into the application logic without effect. Similarly, signals from the application logic pass through the corresponding BSCs to each separate functional output pin without effect. Thus, the normal operation of the integrated circuit remains unaffected by the BSCs.
In addition to its normal data input and output, each BSC has a test data input and test data output (also known as test access ports) connected so that each bit of a test vector applied to the test data input is serially shifted to the test data output of the BSC during operation thereof in a test mode. Also, the test data input of each BSC is linked to its normal data output so the test vector bit, shifted into the BSC during testing, can be applied to its normal data output.
In certain circumstances, rather than testing an IC or CPU, an integrated circuit""s (IC""s) or a central processing unit""s (CPU""s) mode of operation may need to be changed after it has shipped to customers. This need may be due to problems discovered after development testing or for performance enhancements being applied after a system is delivered to the customer. The JTAG port (also known as a test access port), rather than being used merely for testing purposes, also is commonly used in International Business Machine Corporation""s and in other vendor""s products to initialize the major ICs and CPU(s) prior to startup.
When a computer system needs corrective action via the test access port, the device must first be identified. In the case of a CPU, the CPU identification number is normally scanned out and compared with a list of possible identification numbers. When a candidate identification number is found, the corrective action can be taken by scanning new data into the CPU. If the CPU is not a candidate for corrective action, then no scanning in of new data is performed.
In the case of scanning an identification number, the action is time consuming and requires a large and complex program to first scan in an identification number and then compare that number with a list of candidate numbers for corrective action. Therefore, it is desirable to have a method and system for efficiently determining the identity of an integrated circuit or CPU that is less time consuming and requires a smaller and less complex program to perform the task than currently available methods and systems.
The present invention provides a method in a data processing system for identifying a circuit. In a preferred embodiment, a set of bits, with a defined chain length, are shifted into the circuit one bit at a time. The bits shifted out from the circuit are compared to the bits, from the set of bits, shifted into the circuit to determine if the circuit corresponds to a first type circuit. The comparing step is accomplished before all bits in the set of bits have been shifted into the circuit. If the circuit is not a first type circuit corresponding to the set of bits shifted into the circuit, then the shifting of bits into the circuit is discontinued and the process is repeated with a second set of bits corresponding to a second circuit type until the circuit type has been identified.